1. Field of the Invention
The invention pertains generally to chip carriers, and more particularly to a chip carrier having a circuitized surface which is at least partially covered by a protective, ultraviolet (UV) radiation cured coating.
2. Description of the Related Art
One type of semiconductor chip package includes one or more semiconductor chips mounted on a circuitized surface of a substrate, e.g., a ceramic substrate or a plastic substrate. Such a semiconductor chip package, conventionally termed a chip carrier, is usually intended for mounting on a printed circuit card or printed circuit board. If, for example, surface mounting is to be used, then the chip carrier will conventionally include a lead frame or edge clip which is mechanically and electrically connected to electrical contact pads formed around the periphery of the chip-bearing, circuitized surface of the substrate.
A relatively high density of chip connections is readily achieved by mounting one or more semiconductor chips on the circuitized surface of a chip carrier substrate in the so-called flip chip configuration. In this configuration, the chip or chips are mounted face-down on solderable metal pads on the substrate using solder balls. However, the coefficient of thermal expansion (CTE) of, for example, a silicon chip is significantly different from the CTE of a ceramic substrate or plastic substrate. As a consequence, if a chip carrier is subjected to thermal fluctuations, then the solder ball connections will be subjected to significant stresses, which tend to weaken, and reduce the fatigue life of, the solder ball connections. Significantly, this problem is readily overcome by encapsulating the solder balls in an encapsulant having a CTE which is within 30 percent of the CTE of the solder balls. Useful such encapsulants have a composition which includes, for example, an epoxy binder, e.g. a cycloaliphatic epoxide binder, and a filler, e.g. high purity fused or amorphous silica, as disclosed in U.S. Pat. No. 4,999,699, the disclosure of which is hereby incorporated by reference. As noted in this patent, the binder should have a viscosity at room temperature which is no greater than about 1000 centipoise and the filler should have a maximum particle size which is no greater than 31 microns. Moreover, the binder should constitute about 60 to about 25 percent by weight of the total of binder and filler, while the filler should constitute about 40 to about 75 percent by weight of the total.
The circuitry on the circuitized surface of a chip carrier substrate, and to a lesser extent the chip or chips mounted in a flip chip configuration on the circuitized surface, need to be protected from mechanical and environmental hazards. One technique for achieving such protection is to mount a ceramic cap over the chip or chips and at least a portion of the circuitry on the circuitized surface. While the use of such a ceramic cap for achieving mechanical and environmental protection is effective, its use significantly increases the cost of the chip carrier. Moreover, the presence of the ceramic cap precludes the possibility of directly mounting a heat sink on the chip or chips in order to dissipate the heat produced by the chip or chips. Rather, the heat sink is necessarily mounted on the ceramic cap, and a thermal grease must then be provided between the upper surface of each chip and the ceramic cap to achieve good thermal contact between the chip or chips and the heat sink. While this procedure is effective for dissipating heat, it would be more convenient if the heat sink could be directly mounted on the chip or chips.
It has been proposed that the circuitry on the circuitized surface of a chip carrier substrate be covered by a coating having a composition which includes an epoxy binder and a filler, in order to provide mechanical and environmental protection for the circuitry at a relatively low cost. Such filled epoxy coatings have been applied to the upper (non-circuit bearing) surfaces of chips and have proven to be useful. However, it has been recognized that to be useful as a protective coating for the circuitry on the circuitized surface of a chip carrier, such a filled epoxy coating would have to: (1) be capable of withstanding a standard, accelerated thermal aging test, in which the coating is thermally cycled between 0 degrees Centigrade (C) and 100 degrees C., at a frequency of three cycles per hour, for at least 2,000 cycles, without exhibiting internal cracks or cracks at the interface with the solder ball encapsulant, which cracks are undesirable because they allow water and other undesirable chemicals to enter and corrode circuitry; (2) be hydrophobic, for the reason given above; (3) be capable of withstanding a second standard thermal cycling test, usually referred to as the "ship shock" test, in which the coating is thermally cycled from -40 degrees C. to +65 degrees C., at a frequency of one cycle per hour, for at least ten cycles, without cracking or delaminating from the chip carrier substrate; (4) exhibit a low concentration of ions, typically achieved by ensuring that the concentration of chloride ions is less than ten parts per million, to avoid circuitry corrosion and conductor migration, the latter phenomenon leading to undesirable short circuits; and (5) be relatively quickly, and thus conveniently, cured.
Significantly, when filled epoxy coatings of the type referred to above have been extended from the upper surfaces of chips on the circuitized surfaces of chip carriers to the circuitry on the circuitized surfaces of chip carrier substrates of significant size, e.g., 36 mm.times.36 mm, these coatings have proven not to be useful. That is, when these coatings have been subjected to the accelerated thermal aging test, described above, they invariably exhibited internal cracks or cracks at the interface with the solder ball encapsulant. In addition, these coatings are generally hydrophobic. Moreover, when subjected to the "ship shock" test, described above, these coatings have invariably cracked or delaminated from the chip carrier substrates. Further, these coatings are cured by being baked in an oven for a significant period of time, e.g., three hours, which is time consuming and inconvenient.
Thus, those engaged in the development of chip carriers have sought, thus far without success, protective coatings for the circuitry on the circuitized surfaces of chip carriers which are: (1) relatively inexpensive; (2) capable of withstanding standard thermal cycling tests without cracking and without delaminating to provide effective mechanical and environmental protection for the circuitry; (3) hydrophobic; (4) exhibit a low concentration of ions, exemplified by the concentration of chloride ions being less than ten parts per million; (5) relatively quickly and therefore conveniently cured;and (6) permit heat sinks to be directly mounted on chips.